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5. Conclusion and outlook
Hardware techniques to support the implementation of power management in embedded electronic circuits are diverse and locally efficient. To achieve real energy efficiency, a number of issues need to be addressed:
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The organization of a functional architecture according to a power management structure must be thought through in its entirety;
For example, inserting a multitude of power control mechanisms locally can become counter-productive, as it is then difficult to manage them efficiently at system level.
The insertion of power management mechanisms affects functional performance and can also lead to logic errors if all precautions are not taken. Functional verification is thus a complex task for a circuit optimized for power consumption;
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Conclusion and outlook
Glossary
Bibliography
Websites
ITRS, International Technology Roadmap for Semiconductors, ITRS Reports: http://www.itrs2.net/itrs-reports.html (2011 Edition, System Drivers, 2012 Update Overview)
IEEE Standard 1801-2015 UPF, ...
Standards and norms
IEEE Unified Power Format (UPF) for Design and Verification of Low-Power, Energy-Aware Electronic Systems, Standard IEEE 1801, 2015.
Extensions to the IEEE 1685™-2009 IP-XACT standard to describe a power management structure at the RTL level have been proposed:
Directory
Documentation – Training – Seminars (non-exhaustive list)
ECOFAC Thematic School: Thematic School on Low-Consumption Design for Embedded and Real-Time Systems, http://gdr-isis.fr/news/2148/121/Ecole-Thematique-Conception-Faible-Consommation-pour-les-systemes-embarques-et-temps-reels.html
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