Overview
ABSTRACT
In this article, state-of-the-art SOI technologies and their prospects are presented. Materials and the major advantages of SOI circuits are firstly dealt with. Characterization methods and the physical mechanisms that govern the operation of MOS transistors on SOI are described. As SOI technology has high potential for pushing back the boundaries of nanoelectronics, the advantages of the most promising transistors, including alternative channels, multi-gate devices, nanowires and tunneling FETs are reviewed.
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Francis BALESTRA: CNRS Research Directors, Institut de microélectronique, électromagnétisme et photonique (IMEP) Institut Polytechnique de Grenoble (Grenoble INP)
INTRODUCTION
Silicon On Insulator (SOI) technology was invented in the 1960s-1970s to meet the demand for integrated circuits hardened against ionizing radiation. The first material, silicon-on-sapphire (SOS), was followed by a variety of SOI structures. Their common denominator is that, thanks to a buried oxide, they offer perfect dielectric isolation between the circuits' active layer and the bulk silicon substrate. In fact, in a metal-oxide-semiconductor field-effect transistor (MOSFET), only the surface layer of silicon, 0.1 to 0.2 µm thick (i.e. less than 0.1% of the total thickness of the silicon wafer), is really useful for electron transport. The rest of the wafer is responsible for undesirable parasitic effects, which can be avoided by using an SOI-type solution .
Since the early 1990s, the development of new SOI materials and the explosion of portable electronic devices have promoted SOI as the technology of choice for the manufacture of low-power, high-frequency components.
We describe the state-of-the-art in SOI technologies, starting with methods for synthesizing the main materials. The key advantages of SOI circuits over conventional devices on bulk silicon are presented, before we take a closer look at typical components already manufactured on SOI. Characterization methods, both in situ and based on component inspection, are discussed. We'll see that the physical mechanisms governing the operation of partially or totally deserted MOS transistors on SOI are quite different from those usually encountered in MOSFETs ("Metal Oxide Semiconductor Field Effect Transistor") on bulk silicon. SOI has great potential for pushing back the frontiers of micronoelectronics, both through the miniaturization of conventional MOS transistors and through the innovative architectures it can accommodate.
This work was carried out at the IMEP-LAHC laboratory at Grenoble Polytechnic Institute (Grenoble INP). We would like to thank our colleagues – at LETI, STMicroelectronics, SOITEC and –, the carriers of the SOI virus, for all they have taught us.
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KEYWORDS
MOSFET | silicon-on-insulator | multigate | nanowire | strain Si
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