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4. Encapsulation processes
There are two distinct packaging families:
individual, at chip level: after cutting out the manufacturing substrate, each component is extracted and assembled separately in its final package. There are many different types of packaging, most of which have been developed to meet specific application needs and, of course, performance expectations. To achieve this, different types of enclosure (metal, ceramic, plastic) are used, with the emphasis on hermetic sealing. There is a wide variety of enclosures and manufacturers;
wafer scale packaging: this process enables chips to be packaged collectively before the manufacturing substrate is cut, thereby reducing costs and reducing the size of the final component before assembly. It is often likened to wafer level packaging.
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Encapsulation processes
3D integration
Bibliography
Publications and reviews
IEEE Transactions on Components, Packaging and Manufacturing Technology, https://www.cpmt.org
Chip Scale Review – Haley Publishing – https://www.chipscalereview.com
Électronique Mag – Tracks and tablets – Éditions Alain...
Events
ECTC (Electronic Components and Technology Conference) organized by IEEE CPMT – http://www.ectc.net
IMAPS International Symposium on Microlectronics http://www.imaps.org
Standards
IPC: Association Connecting Electronics Industries http://www.ipc.org/
JEDEC (Joint Electron Device Engineering Council) – http://www.jedec.org
Directory
International networks – Organizations – Federations – Associations (non-exhaustive list)
ITRS – International Technology Roadmap for Semiconductors – http://www.itrs.net/home.html
iNEMI – International Electronics Manufacturing Initiative – http://www.inemi.org
...Semiconductor market trends
Little by little, the conventional type of individually packaged chips is evolving towards more compact solutions, improving performance and enabling greater functionality. Table 1 shows the expected evolution of package type between 2011 and 2018...
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