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ABSTRACT
The emergence of new integration concepts and the use of collective methods to produce electronic components have had a major influence on the evolution of packaging and interconnection processes. This article gives an overview of the main integration concepts, attendant challenges and different technological approaches. Some specific difficulties associated with these new integration concepts are also discussed.
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Gilles POUPON: International Expert - CEA-LETI, Minatec, Grenoble, France
INTRODUCTION
The penetration of electronics in virtually every segment of society (communications, transportation, education, agriculture, entertainment, healthcare, environmental controls, research and defense) is contributing to the acceleration of technological processes for making components and, consequently, their integration. Meeting the diversity of demand, at lower cost and with better performance, is impossible without major changes in the architecture, materials and packaging processes of electronic components and modules. These new packaging technologies are called "system-in-package", "wafer level packaging", "3D integration", "through silicon vias" and "interposers". As the need for components continues to grow, two major trends must be addressed: firstly, the reduction in the size of electronic components ("more Moore"), and secondly, the increase in functionality ("more than Moore"). To achieve this, innovation requires the development of new technologies, the emergence of new levels of integration, the extension of existing technologies to new applications and, of course, the evolution of electronic components.
A glossary and table of acronyms are presented at the end of the article, and readers are invited to refer to them as they read on.
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KEYWORDS
packaging | interconnections | microsystems | flip chip | wafer level packaging
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Packaging and interconnection processes for electronic components
Background and developments
Bibliography
Publications and reviews
IEEE Transactions on Components, Packaging and Manufacturing Technology, https://www.cpmt.org
Chip Scale Review – Haley Publishing – https://www.chipscalereview.com
Électronique Mag – Tracks and tablets – Éditions Alain...
Events
ECTC (Electronic Components and Technology Conference) organized by IEEE CPMT – http://www.ectc.net
IMAPS International Symposium on Microlectronics http://www.imaps.org
Standards
IPC: Association Connecting Electronics Industries http://www.ipc.org/
JEDEC (Joint Electron Device Engineering Council) – http://www.jedec.org
Directory
International networks – Organizations – Federations – Associations (non-exhaustive list)
ITRS – International Technology Roadmap for Semiconductors – http://www.itrs.net/home.html
iNEMI – International Electronics Manufacturing Initiative – http://www.inemi.org
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Little by little, the conventional type of individually packaged chips is evolving towards more compact solutions, improving performance and enabling greater functionality. Table 1 shows the expected evolution of package type between 2011 and 2018 for integrated circuits. In 2018, despite annual growth of around 15% per year, flip chips will still...
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