1. From one instruction to several instructions per cycle

The acceleration of processors has always been the main motivation of designers. Pipelined scalar processors aimed to achieve an execution rate of one instruction per clock cycle (IPC = 1), using the techniques described in the article [H 1 004] . To execute several instructions of a sequential program per clock cycle (IPC > 1), two approaches are possible: the VLIW approach

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From one instruction to several instructions per cycle

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page Out-of-order superscalar processors

A brief history of the "restricted data stream" concept

Bibliography

(1) - THORNTON (J.) - Design of a Computer. - The Control Data 6600.
(2) - TOMASULO (R.M.) - An efficient algorithm for exploiting multiple arithmetic unit. - IBM Journal Research and Development, pp. 25-33 (January 1967).