VLIW processors

This article examines the main features of processors with very long instruction words, generally referred to as VLIW (Very Long Instruction Word). A VLIW processor uses the instruction parallelism existing in a sequential program to start the execution of several elementary instructions, which make up the very long instruction word, at each clock cycle. Unlike superscalar processors, where the hardware dynamically determines which instructions can be executed simultaneously, VLIW processors rely totally or mainly on the compiler to constitute the very long instruction word. This characteristic helps explain why these processors perform best when the program behavior is known at compile-time, which is often the case for signal and image processing (DSP).

After a brief history of VLIW processors, the article presents the principles of VLIW execution. A "pedagogical" processor, close to the characteristics of existing VLIWs, is used to illustrate the essential features facilitating the use of the software pipeline to execute elementary instructions belonging to different iterations of a computation loop at each clock cycle. Details are given of how to make the execution of elementary instructions conditional, and how to handle multi-cycle computation instructions, with and without "spinning registers".

Three examples of VLIW processors are then presented, from the pure VLIW approach where the compiler controls all dependencies to approaches mixing VLIW features with hardware dependency control. The first example is the TMS320C6x family of signal processors from Texas Instruments, with successively C62 and C67, C64, C64+ and C674, then C66x. These processors are widely used as DSP processors, offering excellent performance and low power consumption. The second example is TigerSharc, which combines VLIW and superscalar features. A competitor to the TMS320C6x in the early 2000s, this processor has had no successor since. The third example is the EPIC architecture implemented in Itanium processors. This architecture distinguishes between parallel instructions defined by the compiler and the 128-bit long instruction (3 elementary instructions). The hardware decides which parallel instructions can actually start each cycle. VLIW features (predicated instructions, rotating registers, etc.) and hardware features (branch prediction, early memory accesses) are described in detail. Designed by Intel and HP to supplant superscalar processors with unordered execution, EPIC and Itanium processors failed to achieve this goal and have now been abandoned by Intel.

The VLIW approach has been very successful with DSP processors. It is also widely used for signal processing coprocessors in systems-on-a-chip. It is also a viable solution for low-power multi-core...