Multi-pipeline superscalar processors

This article examines the main features of multi-pipeline superscalar processors, often referred to as superscalars in sequence. A superscalar processor uses the instruction parallelism existing in a sequential program to start the execution of several instructions at each clock cycle. The hardware determines which independent instructions can be started simultaneously in different pipelines, because the necessary operators are available and the operands are ready. The use of multiple execution pipelines already exists in scalar processors, which can only start a single instruction per cycle due to the differences in execution times between the majority of integer and float instructions. The problem of controlling data dependencies is therefore already dealt with in scalar processors, and this treatment is recalled. With superscalar processors, hardware problems are accentuated on many points: register bank, cache access, branch prediction, instruction acquisition. In the multi-pipeline model, the hardware gathers instructions in groups of 2 or 4, and all instructions in one group must be issued before instructions in the next group are issued. Examples of the techniques used are given with Intel's Pentium and Atom, Digital's 21064 and 21164, ARM's Cortex A8 and IBM's Power 6 core. Techniques used to overcome the limitations of strict group-by-group booting are detailed.

From a raw performance point of view, "in-order" superscalars are less efficient than "restricted data flow" superscalars, often referred to as "unordered" superscalars, which search for executable instructions in a much larger window than a group of 2 or 4 instructions. For the same manufacturer and CMOS technology, the two approaches can be compared in terms of computing time, chip area and power dissipation. The comparison is presented for two MIPS processors, two IBM cores and ARM cores. At equivalent clock frequencies, the "out-of-order" version always performs better, but the "in-order" version consumes less power, uses less chip area and generally has the best performance per watt or per GHz. In-order" superscalars are therefore a good solution for embedded applications requiring more than the performance of scalar processors, but with less surface area and lower power consumption than the highest-performance solution.