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Article | REF: E2461 V2

Test of integrated digital circuits - Design For Testability

Authors: Mounir BENABDENBI, Régis LEVEUGLE

Publication date: May 10, 2022

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3. Examples of the use of design-for-testability techniques

Most of the Design For Testability (DFT) techniques mentioned in this article are now used in all complex circuits, even (if not especially) in those produced in very high volumes. Memory self-tests and scanpath implementation can be found in virtually every product. Standard compatibility IEEE 1149.1 is usually guaranteed, as each circuit is mounted on a card.

It's very difficult to obtain test specifications from manufacturers for the integrated circuits they produce, as this information is highly sensitive. Nevertheless, to give the reader a clearer idea of what is actually implemented in industry, here are two examples of general-purpose microprocessors from the 2000s. The first example in particular gives an idea of what is acceptable in terms of the extra surface area introduced by testing,...

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