Instruction sets: SIMD and vector extensions

Since the second half of the 1990s, the main instruction sets (Intel IA32 and Intel 64, ARM, IBM, etc.) have introduced SIMD extensions. The essential features were presented in the article [H 1 200] . While Intel has continued to increase the size of SIMD registers from 64 bits to 128, 256 and 512 bits, the other extensions still have 128-bit SIMD registers. Instead of extending the Neon extension to 256 bits, ARM has chosen to define a new extension called SVE (Scalable Vector Extension), which is in fact a vector extension.

We present the difference between SIMD and vector extensions. In a SIMD extension, for a given operation, there is a different instruction for each SIMD register size, for each size (8, 16, 32, 64 bits) and each data type (signed or unsigned integers, floats). In a vector extension, there is only one instruction per operation: vector length and configuration registers define the length of the vector registers, the nature of the elements and the number of elements covered by the operation defined by the instruction. On the DAXPY benchmark, the number of instructions in the benchmark (static code) and the number of instructions executed are compared.

The evolution of SIMD extensions is examined. In addition to increasing register size (256 bits for AVX in 2008, 512 bits for AVX-512 in 2013), Intel extensions saw the introduction of vector features found in vector machines such as the Cray-1 (1976). AVX-2 introduces gather and scatter instructions, which allow memory access with non-unitary steps, whereas pure SIMD only allows access to successive memory words. AVX-512 introduces mask instructions, meaning that the instruction operates according to a mask register, enabling selection of the elements to be operated on. The evolution of Intel SIMD extensions results in a huge increase in the number of instructions. The variable size of Intel instructions makes this possible, at the cost of an increase in the number of instruction bytes (2 to 3 for AVX, 4 for AVX-512). On the other hand, this is a problem for fixed-size instruction sets, such as ARM, where the number of opcodes is limited.

The two main vector extensions are presented: ARM's SVE extension and the vector extension of the RISC-V open source instruction set. The organization of vector registers and configuration registers, as well as the major instruction classes, are detailed.

The vector approach uses far fewer instructions. Another advantage...