Overview
ABSTRACT
The objective of this article is to present a state-of-the-art methodology regarding the EMC development. After reviewing the development cycle in section V, we will then proceed to a description of the various steps of the upwards approach on which design specifications are to be grounded . Although this state -of-the-art method prevents the occurence of major design errors, certain rules are inapplicable due to mechanical, thermal and placement constraints. They thus have to be specifically adapted and justified through modelling. The final development stage consists of the Test Plan drafting which is to guarantee reproducibility results.
Read this article from a comprehensive knowledge base, updated and supplemented with articles reviewed by scientific committees.
Read the articleAUTHORS
-
François de Daran: EMC expert - SAFRAN – Sagem Défense et Sécurité
-
Frédéric Lafon: Senior Expert CEM - Head of EMC expertise at VALEO
-
Thierry SEGOND: EMC expert - SAFRAN – Sagem Défense et Sécurité
INTRODUCTION
EMC design is a complicated art, at the interface between different disciplines such as electronics, microwave, electromagnetism and mechanics. It is therefore important for the designer to rely on a working methodology that will enable him to integrate these heterogeneous constraints. The steps in this methodology will enable him to set up and justify design specifications based on know-how and modeling and simulation tools. At the end of the design phase, it will also be necessary to precisely define the qualification tools and methods in the "Test Plan", so as to guarantee the representativeness and repeatability of the tests.
The routing of an electronic board begins with an analysis of the place reserved for it within an existing mechanical system. Since this mechanism may or may not be metallic, we need to know how to use these properties to improve the behavior of the electronic board with regard to high-frequency electromagnetic interference emissions, as well as external aggression.
PCB routing is also guided by electrical safety regulations (Low Voltage Directive), which introduce the notion of galvanic isolation.
The number of layers allocated in the board guides the choice of using a complete ground plane or a mesh. In addition, current flows in the ground plane have an impact on the segregation rules between disturbance-generating functions, such as high-speed digital electronics, and sensitive functions, such as low-level analog functions. Great importance must be attached to the design of this ground plane, which provides the necessary protection in terms of both emission and immunity.
However, the use of generic routing rules does not guarantee the required EMC performance. What's more, due to constraints other than EMC, these generic rules are generally not applicable without derogation. Modeling, calculation and simulation are the most appropriate ways of validating routing choices or filter sizing. Examples of equivalent component models are presented and used to describe this approach.
The EMC Test Plan is the document on which all EMC testing is based. It must enable a qualification campaign to be carried out while eliminating the risks associated with misinterpretation of specifications or incorrect use of test equipment. To achieve this, it includes a large amount of information specific to the equipment to be qualified, such as a description of product operation or feared events. In addition, it must contain as much information as possible to guarantee the reproducibility...
Exclusive to subscribers. 97% yet to be discovered!
You do not have access to this resource.
Click here to request your free trial access!
Already subscribed? Log in!
The Ultimate Scientific and Technical Reference
KEYWORDS
EMC | EMC design
This article is included in
Electronics
This offer includes:
Knowledge Base
Updated and enriched with articles validated by our scientific committees
Services
A set of exclusive tools to complement the resources
Practical Path
Operational and didactic, to guarantee the acquisition of transversal skills
Doc & Quiz
Interactive articles with quizzes, for constructive reading
EMC design methodology
Bibliography
Standards and norms
- Electronic design automation libraries – Part 1 – Input/output buffer information specifications (IBIS version 3.2) - IEC 62014-1 - 2001
- EMC IC modelling part 2: Models of Integrated Circuits for EMI behavioural simulation – Conducted Emission modelling - IEC 62433-2 - 2008
- Integrated Circuit EMC IC modelling Part 4: ICIM -CI, Integrated Circuit Immunity Model, Conducted Immunity - IEC 62433-4 - 2009 ...
Exclusive to subscribers. 97% yet to be discovered!
You do not have access to this resource.
Click here to request your free trial access!
Already subscribed? Log in!
The Ultimate Scientific and Technical Reference