5. Co-design methodologies

5.1 General

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5.1.1 Design abstraction levels

When co-designing a system-on-a-chip, the time and accuracy required to evaluate different scenarios largely depend on the level of abstraction considered. For example, an evaluation at transaction level (TLM) is significantly faster than one at register transfer level (RTL). This is due to the reduced level of architectural detail considered in TLM compared to RTL. On the other hand, RTL offers greater precision in terms of the reasoning that the designer has to apply. In...

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Bibliography

(1) - BENVENISTE (A.), CASPI (P.), EDWARDS (S.A.), HALBWACHS (N.), LE GUERNIC (P.), DE SIMONE (R.) - « The synchronous languages twelve years later ». - Proceedings of the IEEE, 91 (1) : 64-83 (January 2003).
(2) - AUGUIN (M.), SENTIEYS (O.) - Conception de...